This invention relates to arrays of integrated circuit chips and methods by which they are electrically connected into and then interacted with by their incorporating systems. More particularly it provides an interaction coordination scheme for a very efficiently wired array of like chips. The scheme uses bidirectional (i.e. rightward versus leftward) sequential designation as a means of interacting with one chip at a time, and also employs means for globally programming the desired sequential direction into all member chips of the array when the sequential designation means are paradoxically self obstructed by an initial "directional chaos" condition.
Many systems require unique data to be written into and read from each of a plurality of like chips. In a typical system where the electrical line count is critical, data and clock terminals (pads) of multiple chips are bussed onto a single set of digital lines and are also chained together in a daisy chain manner. The appropriate chaining logic is designed into each chip and a set of chaining pads--one an input and the other an output--are added to each chip. The chaining output of one chip is connected to the chaining input of the following chip and its chaining output is connected to the chaining input of the following chip and so forth until all of the member chips are serially chained together in this way.
The member chips may be sequentially interacted with (i.e. written to or read from) individually by an operational procedure which is known as token passing. Simple token passing schemes typically use a shift register or ring counter to shift, say, a 1 through a field of 0s where the 1 is used to select elements one at a time. (this is not to be confused with "token ring" schemes). In the present context, the above mentioned chaining logic of a chain of like chips forms a manifest shift register or operational equivalent, which spans across the chain of chips. Multiple internal token passing stages may or may not be designed into each chip.
When a specification exists for chips of a particular design to have the capability of operating within a bussed array in which they must be interacted with sequentially using, say, a rightward progression, and for chips of the same design to also be capable of operating within an array which requires a leftward sequential progression, bidirectional token passing means would expectedly be used. Direction control logic and a dedicated (i.e., single purpose) direction control input would typically be added to each chip. Such logic, responsive to the applied logic level of the direction control input, would simultaneously change the I/O modes of both chaining pads so that output becomes input, and input becomes output. Such a chip could be used within applications which require sequentially designated interaction to progress in either direction.
The dedicated direction control inputs of such member chips of a "chained and bussed" array could then be strapped to digital power within an array which requires that the chips be interacted with sequentially in one direction, or to digital ground within an array which requires sequential progression to occur in the opposite direction. An alternative wiring method would be to buss these direction control inputs to a direction control line which would be run to the control sector of the incorporating system. The system could then command a reversal of the token passing direction at any time.
The above stated direction control means objectionably adds one more pad to each member chip, and adds a conductor line to an array of chips for which the requirement of remotely dictated reversibility of its token passing direction exists.
One place where a bidirectional sequentially coordinated chip interaction requirement exists is in a chained and bussed array of light emitting diode (LED) driver chips on a LED print-bar in a printer. The stated scheme of adding dedicated direction control inputs and a direction control line is objectionable on a print-bar however, because pad and electrical conductor line quantities are extremely critical for size and cost reasons.
When consideration is given to the addition of an on-chip direction control storage element (e.g. latch or flip-flop) which would be programmable via the address and data bus--as an alternative to the addition of a dedicated direction control input--a paradox becomes apparent; any attempt to sequence through an array of chips, for the purpose of initially programming their direction control storage element, would be obstructed by an ensuing directional chaos condition which would be realized after powering up the array. This is because the logic state of the direction control element of each member chip would be unpredictable and hence conflict between the chips would be expected. The direction control elements can not be programmed because they had not yet been programmed (a self obstructing predicament).
One expected design solution which might be applied to the programmable direction control concept for the purpose of precluding the stated programming paradox, would be to additionally include on-chip power-up initialization circuits which would initially set the direction control elements of each chip to a predetermined state. Objectionably, this would require the addition of more extensive logic in order to facilitate the contradictory and cumbersome process of sequencing through an array of chips in the default direction, for the purpose of programming them to normally sequence in the opposite direction. It would also require the addition of an on-chip RC circuit.
What is needed is token passing direction control means for a chained and bussed array of like chips which does not require the addition of any more pads or extensive logic or RC circuits to each LED driver chip, or add more electrical conductor lines to a print-bar.